This invention relates to a structure of a semiconductor integrated circuit in which MOS field effect transistors of the complementary type are integrated.
The semiconductor integrated circuit of complementary type MOS field effect transistors has such a structure that a P-type well region is formed in an N-type silicon substrate with N-channel MOS field effect transistors (hereinafter referred to as "N-MOS FETs") formed in the P-type well region and P-channel MOS field effect transistors (hereinafter referred to as "P-MOS FETs") formed in the N-type silicon substrate. The gate electrodes and the drain electrodes of a P-MOS FET and an N-MOS FET are connected in common, respectively, to form and inverter circuit. A supply voltage is applied between the source electrodes of the two FETs. The common gate electrode receives an input signal of the inverter, and the inverter output is derived from the common drain electrodes. Where the inverter circuit is employed as an input buffer amplifier, the common gate electrode of the inverter circuit is connected to an input terminal provided on an integrated circuit chip. Where the inverter circuit is used as an output amplifier, an output terminal provided on the integrated circuit chip is connected to the common drain electrodes of the inverter circuit. When the integrated circuit chip is being not practically used, for example, in storage, static charges are often accumulated on the input terminal and/or the output terminal of the chip. If a part of the chip happens to touch a ground potential, the accumulated static charges flow to the ground, and thus the gate insulating films of the MOSFETs of the input inverter buffer is destroyed or a PN-junction between the drain region of the P-MOS FET and the substrate or between the drain of the N-MOS FET and the P-well region is destroyed in the output amplifier.
To protect the gate insulating films and the PN junction from being destroyed, respective opposite conductivity type regions are formed in the N-type silicon substrate and in the P-well region and connected to the input or output terminal to work as two protective diodes. The two protective diodes are practically connected in series between two power terminals. If the static charges are accumulated on the input terminal or the output terminal and either one of the power terminals is touched to a ground potential, a discharge current flows through either one of the protective diodes. Thus, MOS field effect transistor can be protected from being destroyed.
However, large junction areas cannot be taken for the protective diodes formed in the N-type silicon substrate and the P-well region. Therefore, their current capacities are small. Consequently, the protective diode comes to be destroyed by the static charges accumulated to some degree or over, and thus the integrated circuit itself becomes of no use.
Further, a high impurity concentration region is usually prepared as a channel stopper region at the surface of the N-type silicon substrate and the P-well region to prevent an inducement of a parasitic conductive channel at the surface of the substrate. The high impurity region is normally formed shallower than source and drain regions of the FET's through another diffusion process. Therefore, if the opposite conductivity type regions of the protective diodes and the source and drain regions of the FET's are formed concurrently, there still required is an impurity diffusion process for the channel stopper region.